1. Field
This disclosure is generally related to electronic design automation. More specifically, this disclosure is related to methods and apparatuses for implementing a hierarchical design-for-test (DFT) logic for a modular circuit design.
2. Related Art
Dramatic improvements in semiconductor manufacturing technologies have made it possible to integrate tens of millions of devices onto a single IC (integrated circuit). These developments have given rise to new challenges in the design and manufacture of semiconductor chips. Specifically, chip testing has become one of the most challenging aspects of circuit design.
A circuit-under-test (CUT) can be viewed as a combinational and/or a sequential logic with inputs and outputs. A CUT can be tested by first applying test vectors to inputs of the CUT and capturing its outputs. A fault in the CUT can then be identified by comparing the CUT's actual outputs with a “good” chip's outputs. A common technique for testing chips involves augmenting the CUT with design-for-test (DFT) circuitry, which includes flip-flops that apply test vectors to the CUT and capture response outputs from the CUT. Usually, test vectors are scanned into a set of flip-flops which are coupled with the CUT's inputs. Next, the chip is clocked and the CUT's response values are captured in a second set of flip-flops, which can then be scanned out. Finally, the response values can be used to determine whether the CUT has a fault.
In designs with multiple modules, each module of the CUT can be augmented with dedicated DFT circuitry to test these modules. Unfortunately, in designs with a large number of modules, sharing the test inputs of the CUT is not practical. Specifically, either the test inputs of the CUT have to be partitioned across the set of modules, or the modules need to take turns in receiving test vectors from the test inputs. Both of these approaches have serious drawbacks.
Specifically, partitioning the test inputs can severely limit the number of bits that can be used to represent a test vector for a module, and/or can require a CUT to have an impractically high number of test input pins. Specifically, approaches that use compression scan chains usually require at least five test pins per module. Hence, the partitioning approach would clearly be impractical if the CUT has a large number of modules that use compression scan chains, and each module requires five test input pins on the packaging. The second approach, in which the modules take turns receiving test vectors from the test inputs, is undesirable because it only allows one module to be tested at a time. This can increase the time required for testing a CUT, and can make it difficult, if not impossible, to test interactions between modules of the CUT.